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高级ASIC设计工程师

雇主

NVIDIA

地点

Santa Clara · 美国

待遇

$面议

工作模式

线下

截止日期

1月6日

福利
Equity,Benefits

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岗位摘要

Seeking a Senior ASIC Design Engineer to implement GPU sub-system modules, own micro-architecture, R

岗位职责

NVIDIA is seeking best-in-class
ASIC Design Engineersto design and implement the world’s leading SoC's and GPU's.
This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you’ll be doing:
• As a key member of the Design team, you will be responsible for the implementation of GPU sub-system modules.
• Make architectural trade-offs based on features, performance requirements and system limitations.
• You are expected to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean design.
• Support post-silicon validation activities.
• Work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.
What we need to see:
• Masters Degree (or equivalent experience) in Electrical Engineering or Computer Engineering.
• 8
years of proven experience working on
ASIC design and development.
• Experience in micro-architecture and RTL development of complex designs in Verilog.
• Exposure to Digital systems and
VLSI design, Computer Architecture, Computer Arithmetic,
CMOS transistors and circuits is required.
• Understanding of
ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Prior experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, and/or caches is desirable.
Ways to stand out from the crowd:
• Knowledge of PCI-Express (Gen 3 and above) or CXL protocol is very helpful;
your firsthand design experience on it is a big plus.
• Python, Perl and C/C
programming language experience desirable.
• Good debugging and analytical skills.
• Strong interpersonal skills and ability & desire to work as a great teammate.
NVIDIA is widely considered to be one of the technology world’s most desirable employers.
We have some of the most forward-thinking and hardworking people in the world working for us.
Are you creative and autonomous?
Do you love the challenge of crafting the fastest and most power efficient chips in their class?
If so, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.
You will also be eligible for equity and benefits. Applications for this job will be accepted at least until October 9, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer.
As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

申请条件

Masters Degree (or equivalent experience) in Electrical Engineering or Computer Engineering.
8+ years of proven experience working on ASIC design and development.
Experience in micro-architecture and RTL development of complex designs in Verilog.

雇主简介

NVIDIA is a technology company that designs GPUs and system-on-chip units for gaming, professional visualization, data centers, and automotive markets. The Physics Simulation Team focuses on physics simulation for robotics learning and evaluation.

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