ASIC工程实习生，设计验证

Meta（Meta Platforms）岗位：ASIC Engineering Intern, Design Verification (Silicon Engineering) Responsibilities

Write SystemVerilog test benches and tests that verify digital IP blocks in computer vision and image signal processing pipelines

Build and extend UVM-based verification components (sequences, drivers, monitors, scoreboards) under the guidance of senior engineers

Read design specifications and help write verification test plans, including stimulus, checks, and coverage goals

Run simulations, debug failures, and work out whether each bug is in the design (RTL) or the test bench

Track functional and code coverage, and write directed and constrained-random tests to close coverage gaps

Write Python scripts to automate regressions, triage results, and improve verification workflows

Currently has, or is in the process of obtaining, a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field

Coursework or project experience in digital logic design: logic gates, flip-flops, finite state machines, timing, and clock domains

Programming experience in an object-oriented language (e.g., SystemVerilog classes, C++, Python, or Java)

Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment

Exposure to UVM (Universal Verification Methodology) or another class-based verification methodology

Familiarity with verification concepts such as constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding

Coursework or projects in image processing, computer vision, signal processing, or AI/ML hardware acceleration

Hands-on experience with an RTL simulator (e.g., VCS, Xcelium, Questa, or Verilator) and waveform debugging

A completed digital design or verification project, such as a processor, memory controller, bus or communication interface, or FPGA design

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Currently pursuing or in the process of obtaining a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

Coursework or project experience in digital logic design, including logic gates, flip-flops, finite state machines, timing, and clock domains.