硬件工程师，PCB布局

Define PCB layout architecture and floorplanning strategies for complex, high-layer-count boards used in infrastructure and data center hardware

Establish and own PCB design rules, constraints, and layout guidelines for high-speed interfaces including PCIe, DDR, Ethernet, and SerDes

Lead signal integrity and power integrity analysis in collaboration with electrical engineering teams, driving layout decisions based on simulation results

Drive design-for-manufacturability reviews with contract manufacturers and PCB fabricators to ensure yield, reliability, and cost targets are met

Define and maintain organization-wide PCB layout standards, templates, and best practices adopted across infrastructure hardware programs

Collaborate with mechanical engineers to resolve board-level packaging constraints, thermal management requirements, and enclosure integration challenges

Provide technical guidance to other layout engineers across multiple concurrent infrastructure hardware programs

Partner with supply chain and component engineering teams to evaluate and qualify alternative components and footprints

Lead post-layout verification activities including design rule checks, electrical rule checks, and pre-production board bring-up support

Evaluate and introduce new EDA tooling, layout methodologies, and fabrication technologies to improve design quality and cycle time

8+ years of experience in PCB layout design for high-speed digital systems, including boards with DDR, PCIe, or high-speed SerDes interfaces

8+ years of experience with industry-standard EDA layout tools such as Cadence Allegro, Mentor Xpedition, or equivalent

Experience defining PCB stack-up configurations, impedance control strategies, and design rule constraints for high-layer-count boards

Experience collaborating with signal integrity and power integrity teams to translate simulation results into layout implementation decisions

Experience leading PCB layout efforts across the full product development lifecycle from schematic capture through manufacturing release

Experience designing PCBs for data center infrastructure hardware including server, storage, or networking platforms

Experience establishing layout centers of excellence or defining team-wide PCB design standards across multiple concurrent programs

Meta builds technologies that help people connect, find communities, and grow businesses.

When Facebook launched in 2004, it changed the way people connect.

Apps like Messenger, Instagram and WhatsApp further empowered billions around the world.

Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology.

People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

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Individual compensation is determined by skills, qualifications, experience, and location.

Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable.

In addition to base compensation, Meta offers benefits.

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8+ years of experience in PCB layout design for high-speed digital systems, including boards with DDR, PCIe, or high-speed SerDes interfaces.

8+ years of experience with industry-standard EDA layout tools such as Cadence Allegro, Mentor Xpedition, or equivalent.