硬件工程师，AI加速器模块设计

Own the electrical design and PCB implementation of AI accelerator modules for high-performance, high-power custom silicon (MTIA) and third-party accelerators

Contribute to module requirements and specifications in partnership with ASIC, platform, rack, and systems architecture teams

Execute ASIC package-to-board co-design, including breakout routing, substrate interaction, and escape feasibility analysis for high pin-count devices

Design power delivery networks for high-current loads, including DC-DC topology selection, decoupling strategy, and plane/stackup partitioning

Implement high-speed interface design across PCIe Gen5/Gen6, CXL, DDR5/LPDDR, HBM, and Ethernet up to 800G, including simulation-guided stackup and channel budgeting

Partner with Signal and Power Integrity teams on SI/PI analysis and simulation-to-measurement correlation for your designs

Participate in and prepare module-level design reviews; ensure schematic, layout, and DFM/DFT readiness for your designs

Lead board bring-up and debug; root-cause electrical, power, and interoperability failures and drive design fixes to closure

Work with ODM/JDM partners through NPI-to-mass-production cycles, holding partners to Meta design standards and schedule

Contribute to reusable reference designs, design-rule libraries, and design automation; support publication through the Open Compute Project

Evaluate emerging technologies with industry partners – HDI and advanced substrates, embedded components, novel materials

Collaborate across hardware, firmware, mechanical, thermal, and manufacturing teams to resolve cross-functional issues

6+ years of experience in electrical and PCB design for high-speed, high-power digital systems (servers, accelerators, networking, or HPC)

Experience taking at least one complex custom board or module design from concept through volume production

Proficiency with EDA tools for schematic capture and PCB design (Cadence Allegro/OrCAD, Altium Designer, or equivalent)

Experience with high-speed digital interface design (PCIe, CXL, DDR4/DDR5, HBM, Ethernet 25G+) and SerDes-based channel design

Experience with power delivery network design for high-current loads, including DC-DC topology selection and decoupling strategy

Experience with board bring-up, debug, and failure analysis using oscilloscopes, VNAs, TDR, and power analyzers

8+ years of experience in module or board design for AI/ML accelerators, data center, or HPC hardware

MS in Electrical Engineering with emphasis on electromagnetics, signal integrity, or power electronics

Experience collaborating across hardware, firmware, mechanical, thermal, and manufacturing teams

Exposure to ASIC or GPU package-to-board co-design and breakout routing for high pin-count devices

Contributions to open-source hardware or the Open Compute Project, or external technical publications

Hands-on experience with SI/PI simulation tools (Ansys HFSS, Cadence Sigrity, Keysight ADS/PathWave, or equivalent)

Experience with next-generation interconnect: PCIe Gen6, CXL 3.x, UCIe, scale-up fabrics, or co-packaged optics

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Individual compensation is determined by skills, qualifications, experience, and location.

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BS in Electrical Engineering, Computer Engineering, or a related technical discipline.

6+ years of experience in electrical and PCB design for high-speed, high-power digital systems (servers, accelerators, networking, or HPC).