ASIC验证工程师

Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level

Work with Architecture and Design team to come up with formal specification and implementation

Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level

Provide training for internal teams and mentoring engineers on Formal Verification technology related to Formal Verification Technology

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc

Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques

Experience collaborating with cross-functional teams such as design, architecture, and software to deliver verification milestones

Experience with development of fully automated flows from specification to fully verified designs

Experience interpreting hardware specifications and extracting design behaviors and properties for formal verification

Formal verification experience in clock domain crossing, IP-XACT based register verification and low power

Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW accelerators

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8+ years of experience in Design Verification.

5+ years of experience in Formal Verification.