DPU IO架构师，基础设施芯片

Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management -- from early path-finding through silicon bring-up

Decide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between them

Define the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build on

Work closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs change

Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed

refine architecture to meet the design and PD constraints.

Define architecture to maximize DV complexity including defining specific features to help ease DV

Support Design, DV and PD to resolve interface and integration issues as they come up. Support post-silicon bring-up of the I/O subsystem

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for

Experience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rules

Experience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data Encryption

Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughput

Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM)

Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualization

Experience driving architectural decisions independently and influencing their direction through data

15+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICs

Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows

Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis

Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs

Experience with system-management concepts including server/BMC interactions, and protocols such as I2C, I3C, USB/Ethernet, USB/MCTP, and SPI/eSPI

Experience designing high-performance DMA engines and offload accelerators, such as for cryptography and compression

Experience with post-silicon performance validation and model-to-hardware correlation methodologies

Understanding of Confidential Computing use cases and the related PCIe protocols -- Data Object Exchange (DOE), Security Protocol and Data Model (SPDM), Management Component Transport Protocol (MCTP), and TEE Device Interface Security Protocol (TDISP)

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8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces—register and programming models, D