性能架构师，Reality Labs

Conduct thorough bottleneck analysis of existing and future SoCs to identify areas for improvement

Develop accurate models of IP components, SoC fabric, and DRAM to predict performance and inform design decisions

Analyze system usage behavior of workloads and create micro-benchmarks to evaluate performance

Identify opportunities for optimization and collaborate with hardware teams to solidify HW-SW co-design

Work across disciplines, collaborate with vendors, brainstorm ideas and solutions, develop new methodologies, and coordinate multiple initiatives

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

Experience with SoC architecture, NoCs, memory sub-system, Quality of Service (QoS), and heterogeneous compute principles

Experience deconstructing technical problems, designing performance experiments, analyzing/visualizing data, and sharing detailed analysis in the form of documentation with peers and cross-functional partners

Experience working with cycle-accurate performance models and frameworks for performance architecture evaluations of various SoC components (Accelerators, NoC, DRAM, MMU, etc.)

Experience with bare-metal programming, micro-benchmarking, performance instrumentation, Simpoints, etc

Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)

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Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

8+ years of experience in creating performance models using C/C++ or SystemC.