机器学习硬件验证经理

Lead and manage a team of hardware design verification engineers working on custom ML accelerator silicon, setting technical direction and driving execution against tape-out schedules

Define and own the verification strategy for ML hardware blocks, including compute engines, memory hierarchies, and on-chip interconnects, encompassing simulation and formal verification

Drive functional coverage closure and sign-off criteria across multiple silicon projects, ensuring verification completeness before tape-out

Partner with RTL design and architecture teams to review specifications, identify verification risks early, and influence design-for-verifiability decisions

Collaborate with post-silicon validation and software teams to align pre-silicon verification environments with bring-up and debug infrastructure

Establish and scale verification infrastructure, including UVM testbench development, constrained-random stimulus generation, and assertion-based verification frameworks

Translate organizational strategy into team roadmaps, balancing short-term tape-out deliverables with long-term investments in verification automation and reuse

Communicate verification status, risk assessments, and mitigation plans clearly to engineering leadership and cross-functional stakeholders

12+ years of experience in hardware design verification, including functional simulation, coverage-driven verification, and formal verification of digital logic

5+ years of experience in managing hardware engineering teams, including setting technical direction and driving execution across multiple concurrent projects

Knowledge of SystemVerilog Assertions, X-propagation, UPF-power aware, gate-level simulations

Experience with UVM-based testbench architecture and constrained-random verification methodologies applied to complex SoC or accelerator designs

Experience in driving verification closure for tape-out on custom silicon, including coverage analysis, regression management, and sign-off processes

Experience collaborating with RTL design, physical design, and post-silicon validation teams across the full silicon development lifecycle

Familiarity with emulation platforms and FPGA-based prototyping as part of a pre-silicon verification flow

Experience in verifying ML accelerator hardware components such as matrix multiply units, dataflow engines, or high-bandwidth memory interfaces

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12+ years of experience in hardware design verification, including functional simulation, coverage-driven verification, and formal verification of digital logic.