封装工程师

SI/PI requirements analysis and optimization into product definition — chip floorplan, bump map, power tree structure, and net topology — for HPC and AI silicon built on 2.5D/3D package technology.

Die-Package-Board Co-Optimization (DPCO): Partner with package layout and physical design to converge bump assignment, escape routing, and stack-up decisions across multiple disparate chiplets.

Timing & Budgets: Develop and maintain interface timing budgets and voltage/noise budgets spanning silicon IO PHY, package, and board.

Tool & Flow Development: Improve the accuracy and turnaround time of SI/PI flows through automation and correlation-driven model refinement.

Work across Architecture, ASIC, Mixed Signal, Package, PCB, and System teams to ensure package and system SI/PI performance meets expectation before Gerber out.

Engage foundries and OSATs (e.g., TSMC CoWoS/SoIC, Intel EMIB) and memory suppliers on emerging interconnect and die-stacking standards.

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

Proven understanding of impedance control, transmission line and PDN characterization, feasibility study and create practical design guidelines

Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, Voltage budget, complex SIPI models, frequency, and time domain simulation)

Expertise in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe and etc)

Familiarity with post-Si test environment on memory (HBM/ /DDR4/LPDDR4/DDR5/LPDDR5) or high speed SERDES

Package-level signal integrity and power integrity understanding including silicon, package, and board

Experience using Cadence Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS

Experience with consumer hardware design, review and bring-up process, CAD tools, constraint manager etc

8+ years of experience in SIPI fundamentals, familiar with substrate/PCB design and manufacture process

Experience in collaborating with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams

Solid understanding and experiences in computational electromagnetics and transmission line theory

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Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

8+ years of experience with signal integrity analysis, simulation, and measurement.

Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools.