编译器工程师，图编译器性能优化

Meta（Meta Platforms）岗位：Compiler Engineer, Graph Compiler Performance Optimization Responsibilities

Design, implement, and validate graph-level compiler optimization passes targeting performance within the PyTorch Inductor / FX IR compilation pipeline for MTIA

Profile and analyze deep learning models to identify graph-level performance bottlenecks such as suboptimal fusion boundaries, excessive memory traffic, and scheduling inefficiencies — then develop compiler solutions to address them

Develop and extend automatic fusion strategies to unlock peak hardware utilization across MTIA chip generations

Implement memory optimizations including data placement strategies, memory footprint reduction, and data movement elimination to reduce latency and improve bandwidth utilization

Collaborate with hardware design teams on hardware-software co-design: informing hardware features from compiler needs and rapidly developing compiler support for new chip capabilities

Ensure compiler optimizations are portable and scalable across MTIA chip generations, enabling rapid software bring-up for new silicon

Partner with AI researchers to co-design model architectures and compiler optimizations, ensuring models run performantly on MTIA out of the box

Experience in compiler development, performance optimization, or accelerating deep learning models on hardware architectures

Understanding of deep learning model execution (graphs, operators, data flow) and how compiler transformations affect end-to-end performance

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

A Bachelor's degree in Computer Science, Computer Engineering, relevant technical field and 7+ years of experience in compiler development or accelerating deep learning models on hardware architectures OR a Master's degree and 4+ years OR a PhD and 3+ years of relevant experience

Experience with graph-level compiler optimizations such as operator fusion, graph scheduling, memory allocation optimization, dead code elimination, or constant folding in ML compiler stacks

Experience with PyTorch internals, PyTorch 2.0 compilation stack (TorchDynamo, FX IR, Inductor), or similar ML compilation frameworks (XLA, TVM, MLIR, Glow)

Experience with performance profiling and analysis: identifying compute/memory/I/O bottlenecks, understanding roofline models, and developing systematic approaches to performance tuning

Experience with traditional compiler optimizations (loop transformations, vectorization, parallelization, instruction scheduling) and how they apply to ML workloads

Experience with AI hardware accelerator architectures (GPUs, TPUs, or custom ASICs) and understanding of how hardware constraints inform graph-level optimization decisions

Experience working with deep learning frameworks (PyTorch, TensorFlow, JAX) and understanding their compilation and execution models

Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)

Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies

Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)

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Experience with C/C++ and Python programming.

Experience in compiler development, performance optimization, or accelerating deep learning models on hardware architectures.