硅片CAD与集成工程师

Define and own end-to-end digital implementation methodology including RTL-to-GDS flows, synthesis, place-and-route, DFT insertion, and multi-corner physical signoff

Lead analog mixed-signal physical integration strategy, establishing constraint authoring, floorplanning guidelines, and interface protocols between custom and digital domains

Develop and maintain CAD automation infrastructure using Python, SKILL, and Tcl to reduce manual effort across implementation, tapeout, and regression workflows

Integrate AI and LLM-assisted coding tools into CAD methodology to improve design automation productivity across the silicon engineering organization

Drive physical signoff convergence across timing, power, noise, and design rule checks to produce foundry-ready deliverables on schedule

Establish 3D integration and heterogeneous packaging flows including die-to-die interface planning, cross-die timing closure, and bump/interposer constraint management

Partner with foundry contacts on PDK qualification, design rule interpretation, and process design kit updates for leading-edge technology nodes

Define low-power implementation methodology including multi-voltage domain integration, UPF-based power intent authoring, and power analysis signoff

Provide technical direction to other engineers on CAD methodology decisions, flow architecture, and implementation best practices across multiple concurrent tapeout programs

Communicate implementation status, methodology decisions, and risk assessments to circuit designers, layout engineers, and program leadership

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

8+ years of industry experience in VLSI CAD, physical implementation, or silicon design methodology across multiple technology nodes and tapeouts

Expertise in full RTL-to-GDS digital implementation flows including synthesis, place-and-route, DFT, and multi-corner physical signoff using industry-standard EDA tools

Experience with analog mixed-signal physical integration including constraint authoring, floorplan coordination, and interface management between custom and digital design domains

Proficiency in scripting and automation using Python, SKILL, Tcl, or equivalent languages to build and maintain CAD flow infrastructure

Experience communicating methodology decisions, tapeout risk, and implementation status to cross-functional partners including circuit designers, layout engineers, and foundry contacts

Experience with 3D stacking or advanced packaging flows including die-to-die interface planning, cross-die timing analysis, and heterogeneous integration methodology

Experience with PDK qualification and design rule development in direct collaboration with foundry partners on leading-edge process nodes

Background in low-power design methodology including UPF-based power intent, multi-voltage domain integration, and power signoff for mobile or wearable silicon applications

Familiarity with AI-assisted design tools or LLM-based coding assistants applied to CAD automation or implementation flow development

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Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

8+ years of industry experience in VLSI CAD, physical implementation, or silicon design methodology across multiple technology nodes and tapeouts.