信号完整性工程师，基础设施硬件

Develop next-generation SI/PI solutions across a broad range of Meta platforms, including AI, network, compute, and storage systems

Perform signal integrity simulations, implementation, validation, and test methodologies at the platform, board, and system levels using industry-standard tools such as HSpice, ADS, or Sigrity to validate channel performance and margins

Develop and maintain channel models, IBIS-AMI models, and S-parameter extraction workflows for board-level and system-level SI analysis including end-to-end electrical-optical-electrical channels

Define the next generation of open on- and off-chip interconnect technologies and integrate these into highly scalable, deployable, and maintainable systems

Collaborate with design and manufacturing teams to define stackup requirements, routing constraints, via structures, and impedance targets for multi-layer high-speed designs

Drive lab correlation and validation activities, including TDR, VNA, and oscilloscope-based measurements, to verify simulation accuracy and characterize channel performance

Partner with silicon vendors and internal ASIC teams to evaluate PHY specifications, equalization parameters, and link training behavior for new interface standards

Establish design guidelines, review processes, and SI sign-off criteria adopted across Meta's infrastructure hardware portfolio

Identify systemic signal integrity risks early in the design cycle and drive architectural trade-off decisions with hardware platform and mechanical engineering teams

Mentor other engineers on signal integrity principles, simulation best practices, and measurement techniques to elevate the team's technical capability

Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience

8+ years of experience in signal integrity engineering for high-speed digital systems, including board-level and system-level SI/PI analysis

Experience with PCB board level design and layout, high-speed interconnect and switching using merchant silicon ASICs

Experience with 112G/224G PAM4 SerDes channel design, co-packaged optics, and optical channels, for data center networking applications

Background in open compute or hyperscale data center hardware development with exposure to full platform design cycles from architecture through production validation

Familiarity with IBIS-AMI modeling, channel simulation automation scripting, and statistical eye analysis methodologies

Experience collaborating with silicon vendors on SerDes bring-up, equalization tuning, and compliance testing for next-generation interface standards

Experience with advanced PCB materials, HDI materials and evolving interconnect technologies

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Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.

8+ years of experience in signal integrity engineering for high-speed digital systems, including board-level and system-level SI/PI analysis.